Microarchitecture performance plays a significant role in improving overall system performance. However, with the advent of attacks like Spectre and Meltdown, microarchitecture features that used to contribute to system performance are now causing information leakage thanks to covert, side, and transient channels. At the CASPER research group, we focus on designing (i) secure microarchitectures like caches keeping performance and energy efficiency in mind, and (ii) proposing new microarchitecture attacks.
Active from 2018 Funding: Semiconductor Research Corporation, Qualcomm Faculty Award
People
Biswabandan Panda
Outcome
Yashika Verma, and Biswabandan Panda, “Avenger: Punishing the Cross-Core Last-Level Cache Attacker and Not the Victim by Isolating the Attacker” to appear in the IEEE International Symposium on Secure and Private Execution Environment Design (SEED) 2022
Ajaykumar Kushwaha, Ajay Jain, Mahendra Patel, and Biswabandan Panda, “Golmaal: Thanks to the Secure TimeCache for a Faster DRAM Covert Channel” in DRAMSec@ISCA 2022
Anish Saxena and Biswabandan Panda, “DABANGG: A Case for Noise Resilient Flush-Based Cache Attacks, in WOOT@S&P 2022
Yashika Verma, Dixit Kumar, and Biswabandan Panda, “EnclaveSim:A Micro-architectural Simulator with Enclave Support” to appear in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2022
Tarun Solnaki and Biswabandan Panda, “SpecPref: High Performing Speculative Attacks Resilient Hardware Prefetchers” to appear in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2022 [Winner of MICRO-SRC 2021]
Dandpati Kumar Bhargav Achary, R Sai Chandra Teja, Sparsh Mittal, Biswabandan Panda, and C Krishna Mohan “Inferring DNN layer-types through a Hardware Performance Counters based Side Channel Attack ” in Proceedings of 1st ACM International conference on AI-ML systems, 2021
Pratik Kumar, Chavhan Sujeet Yashavant, and Biswabandan Panda, “DAMARU: A Denial-of-Service Attack on Randomized Last-Level Caches” in IEEE Computer Architecture Letters, 2021
Mriganka Shekhar Chakravarty and Biswabandan Panda, “Introducing Fast and Secure Deterministic Stash Free Write Only Oblivious RAMs for Demand Paging in Keystone” in Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), ISCA 2021
Vishal Gupta, Vinod Ganesan, and Biswabandan Panda, “Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks” in Proceedings of 25th IEEE/ACM Design and Automation Test in Europe (DATE), 2021
Aditya Rohan, Biswabandan Panda, Prakhar Agarwal, “Reverse Engineering the Stream Prefetcher for Profit”, in Proceedings of SILM Workshop on Security of Software/Hardware Interfaces@5th European Symposium on Security and Privacy (Euro S&P), 2020
Biswabandan Panda, “Fooling The Sense of Cross-core Last-level Cache Eviction Based Attacker By Prefetching Common Sense”, in Proceedings of 28th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2019
Dixit Kumar, Chavhan Sujeet Yashavant, Biswabandan Panda, and Vishal Gupta “How Sharp is SHARP?” in WOOT@USENIX SECURITY 2019
