State-of-the-art micro-architectural attacks target different on-chip and off-chip components like processor pipelines, branch predictors, caches, DRAMs, interconnects, etc. One of the solutions proposed recently is to temporally or spatially partition these resources shared among different processes and cores in the form of cache partitioning, DRAM channel partitioning, etc. However, preliminary studies show that this kind of strong isolation at all levels of microarchitecture can lead to a performance overhead in the range of 2X to 30X. Another approach to mitigate this problem is through the randomization of microarchitecture units like randomized branch predictors, caches, and TLBs that make the life of an attacker difficult. Randomization techniques incur minimal performance loss. However, these techniques incur significant storage overhead with additional design complexity. As part of the project, students will explore techniques that can provide strong security guarantees mitigating various microarchitecture attacks without compromising performance and storage overheads.